publications

The high penetration of Distributed Energy Resources (DERs) and the IoT devices in the grid, as a result of policy regulations and economic considerations, physically located everywhere, in all shapes and sizes, both in front (FTM) and behind the meter (BTM) are fundamentally transforming the grid into a decentralized network of new grid assets that participate in multiple hierarchical energy markets. This transformation, however, creates challenges that needs to be managed. In order to adequately capture the transient behavior of the various grid components, detailed component models and Real-Time (RT) simulations are required. Leveraging their inherent parallelism capabilities, FPGA platforms help to achieve high-speed simulation execution, becoming a useful validation and planning tool for power grid management. However, the hardware utilization in these solutions is directly proportional to the size of the network under test, leading to expensive and hardly scalable architectures unsuitable for the simulation of large scale power networks. In this paper, a novel technique is presented, which aims to reduce the FPGA's resources utilization in distribution power grids. There are cases where part of the network under test can be partitioned in a number of identical subnetworks, whose output can be calculated by the same hardware module and thus lead to hardware utilization reduction. As proof of concept of the proposed approach, the implementations of a microgrid with and without applying the partitioning technique are demonstrated and compared in terms of accuracy, simulation speed and FPGA resources utilization.

Smart grid technology is the next step to the evolution of classical power grids, providing robustness, reliability, and security throughout the network, enabling real-time management and control. To achieve these goals, distributed computing (microgrid concept) and intelligent control algorithms, tailored to the nature and needs of the network under study, are necessary. To deal with the vast diversity of power grids, being able to capture the dynamics of any given network, and create tools for network analysis, apparatus testing, and power grid management, an automatic design framework for real-time power system simulators is needed. In this article, a prototype of this approach is presented, employing Field Programmable Gate Array (FPGA) platforms due to their reconfigurability that enables low-power, low-latency, and high-performance designs, as a first attempt towards an open source platform, compatible with the majority of hardware design suites. It comprises two major parts: (i) a user-oriented section, built in Matlab/Simulink; and (ii) a hardware-oriented section, written in Matlab and Very High Speed Integrated Circuit (VHSIC)-Hardware Description Language (VHDL) code. To verify its functionality, two test power networks were given in a schematic format, analyzed through Matlab code and turned into dedicated hardware simulators with the aid of the VHDL template. Then, simulation results from Simulink and the prototype were compared for error estimation. The results show the prototype’s successful implementation with minimal resources utilization, high performance and low latency in the order of nanoseconds in Xilinx 6- and 7-series FPGAs, therefore proving its modularity and efficient use in many different scenarios, meeting low-latency/real-time requirements while enabling further smart grid research.